TOPNAME = top
INC_PATH = $(abspath ./include)
TRACE = --trace

VERILATOR = verilator
VERILATOR_CFLAGS += -MMD --build -cc  \
				-O3 --x-assign fast --x-initial fast --noassert
VERILATOR_CFLAGS += $(TRACE)
BUILD_DIR = ./build
OBJ_DIR = $(BUILD_DIR)/obj_dir
BIN = $(BUILD_DIR)/$(TOPNAME)
WAVE = wave.vcd
ARGS = /home/zhoupu/ysyx-workbench/am-kernels/tests/cpu-tests/build/dummy-riscv64-npc.bin

default: $(BIN)

$(shell mkdir -p $(BUILD_DIR))

# project source
VSRC = $(shell find $(abspath ./vsrc/) -name "*.v" -or -name "*.sv" )
CSRC = $(shell find $(abspath ./csrc/) -name "*.c" -or -name "*.cc" -or -name "*.cpp")

# rules for verilator
INCFLAGS = $(addprefix -I, $(INC_PATH))
LDFLAGS = -lreadline -lSDL2
CFLAGS += $(INCFLAGS) -DTOP_NAME="\"V$(TOPNAME)\""

$(BIN): $(VSRC) $(CSRC) 
#	@rm -rf $(OBJ_DIR)
	$(VERILATOR) $(VERILATOR_CFLAGS) \
		--top-module $(TOPNAME) $^ \
		$(addprefix -CFLAGS , $(CFLAGS)) \
		--Mdir $(OBJ_DIR)  $(addprefix -LDFLAGS , $(LDFLAGS)) --exe -o $(abspath $(BIN))

all: default

sim: $(BIN)
	$(call git_commit, "sim RTL") # DO NOT REMOVE THIS LINE!!!
	@$^ $(ARGS)
	-gtkwave $(WAVE)

run: $(BIN)
	@$^ $(ARGS)

clean:
	rm -rf $(BUILD_DIR)
	rm -f $(WAVE)

.PHONY: default all sim clean run

include ../Makefile
